71. Grams. S. Lin and you can J. B. Kuo, “Fringing-Caused Slim-Channel-Feeling (FINCE) Relevant Capacitance Decisions of Nanometer FD SOI NMOS Devices Having fun with Mesa-Isolation Thru three dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Development away from Bootstrap Approaches to Lower-Current CMOS Digital VLSI Circuits to possess SOC Apps” , IWSOC , Banff, Canada ,
P. Yang, “Door Misalignment Impact Related Capacitance Decisions out of an effective 100nm DG FD SOI NMOS Product with letter+/p+ Poly Top/Base Gate” , ICSICT , Beijing, China
73. Grams. Y. Liu, Letter. C. Wang and you can J. B. Kuo, “Energy-Productive CMOS Highest-Load Rider Routine to the Subservient Adiabatic/Bootstrap (CAB) Way of Lower-Stamina TFT-Liquid crystal display Program Applications” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you will K. W. Su, “CGS Capacitance Sensation regarding 100nm FD SOI CMOS Products that have HfO2 High-k Door Dielectric Provided Straight and Fringing Displacement Effects” , HKEDSSC , Hong-kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Relevant Capacitance Conclusion regarding a good 100nm DG SOI MOS Gizmos with N+/p+ Top/Base Gate” , HKEDSSC , Hong-kong ,
76. G. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Efficient CMOS Highest-Load Driver Circuit to your Complementary Adiabatic/Bootstrap (CAB) Technique for Low-Power TFT-Liquid crystal display System Applications” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you can J. B. Kuo, “An effective 0.8V CMOS TSPC Adiabatic DCVS Logic Routine toward Bootstrap Approach to have Lower-Energy VLSI” , ICECS , Israel ,
B. Kuo, “A book 0
80. J. B. Kuo and you will H. P. Chen, “A minimal-Current CMOS Load Driver towards Adiabatic and you will Bootstrap Tips for Low-Stamina System Applications” , MWSCAS , Hiroshima, Japan ,
83. Meters. T. Lin, E. C. Sunshine, and you can J. B. Kuo, “Asymmetric Entrance Misalignment Effect on Subthreshold Qualities DG SOI NMOS Devices Given Fringing Digital Field effect” , Electron Devices and you will Point Symposium ,
84. J. B. Kuo, Age. C. Sunrays, and you will M. T. Lin, “Study of Door Misalignment Impact on the fresh new Tolerance Current regarding Twice-Entrance (DG) Ultrathin FD SOI NMOS Products Having fun with a tight Model Considering Fringing Electronic Field-effect” , IEEE Electron Gadgets to possess Microwave oven and you can Optoelectronic Programs ,
86. Elizabeth. Shen and J. 8V BP-DTMOS Posts Addressable Thoughts Cell Circuit Produced by SOI-DTMOS Processes” , IEEE Appointment towards Electron Products and you can Solid-state Circuits , Hong-kong ,
87. P. C. Chen and you will J. B. Kuo, “ic Reason Routine Having fun with an immediate Bootstrap (DB) Way of Reasonable-voltage CMOS VLSI” , Globally Symposium into Circuits and Options ,
89. J. B. Kuo and you will S. C. Lin, “Compact Breakdown Design to own PD SOI NMOS Equipment Provided BJT/MOS Impact Ionization to have Liven Circuits Simulator” , IEDMS , Taipei ,
ninety. J. B. Kuo and you can S. C. Lin, “Compact LDD/FD SOI CMOS Product Design Given Opportunity Transport and you may Notice Heat getting Liven Circuit Simulator” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B kissbrides.com Hopp over til nettstedet. Kuo, “Fringing-Caused Burden Minimizing (FIBL) Results of 100nm FD SOI NMOS Devices with a high Permittivity Door Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,
ninety-five. J. B. Kuo and you may S. C. Lin, “Brand new Fringing Electric Field-effect to the Small-Route Perception Threshold Voltage off FD SOI NMOS Gadgets which have LDD/Sidewall Oxide Spacer Structure” , Hong kong Electron Equipment Conference ,
93. C. L. Yang and J. B. Kuo, “High-Temperature Quasi-Saturation Make of Higher-Current DMOS Strength Products” , Hong kong Electron Equipment Appointment ,
94. Elizabeth. Shen and you may J. B. Kuo, “0.8V CMOS Posts-Addressable-Recollections (CAM) Cell Ciurcuit that have a simple Tag-Evaluate Effectiveness Using Majority PMOS Active-Endurance (BP-DTMOS) Techniques According to Standard CMOS Technical for Reduced-Voltage VLSI Solutions” , Globally Symposium into the Circuits and Assistance (ISCAS) Proceedings , Arizona ,